Integrated circuits (“ICs”) are typically formed on a wafer of semiconductor material that is subsequently cut into individual dies. The individual dies, or chips, contain millions of individual elements (e.g. transistors, gates, pastors, diodes, resistors, etc.). While individually these solid-state elements are typically highly reliable, each with a failure rate on the order of one in one trillion devices, the entire chip can fail due to the formation of cracks, fissures, fractures, delaminations, or other dislocations in the IC die. Advanced ICs which utilize a larger number of layers and generate more heat are even more susceptible to die crack or delamination problems.
Detecting cracks and their cause is important to IC fabricators because cracking frequently results in an inoperable IC device. IC fabricators desire to detect cracks as early in the fabrication process as possible so additional process steps are not performed and so corrective actions can be taken at the appropriate process steps to prevent the die cracks.
IC devices that have cracked dies are often returned and the IC fabricator must determine the cause of the crack to determine if it is due to inappropriate customer usage. Diagnosing cracks early allows the fabricator to determine if the crack occurred before delivery to customer and to identify whether the customer is inadvertently causing damage to the IC die.
Heretofore, die cracks have been detected by determining whether a failure of the chip has occurred, and if such a failure has occurred, optically inspecting the IC die for a crack or other defect. Optical detection is a time-consuming process and can require that the die be depackaged or otherwise uncovered to view whether a crack is present. The die crack problems can result in a number of failure modes for the IC device. The cause of the die cracks is often difficult to determine without expensive optical analysis on a large number of failed units. This analysis requires a large amount of time and integrated circuit yields and qualities can suffer while the cause of the die crack problem is being diagnosed.
FIG. 1 of U.S. Pat. No. 6,449,748 shows an example of an implementation of guard rings used to detect die crack problems. The guard rings are provided on test dies. Guard rings are generally composed of conductive lines, usually metal, which are formed in one or more layers of test die. A disconnective segment of the guard ring indicates a crack in that region of the die.
U.S. Pat. No. 6,449,748 notes that it is impracticable to place guard rings in actual chips which are produced and sold to customers (production chips) due to the amount of space required on chip and additional processing for this additional circuitry. According to U.S. Pat. No. 6,449,748, such guard rings are not useful in identifying die cracks in production chips, especially in production chips in which the die crack problem develops later in the process.
Microprocessors manufactured by Advanced Micro Devices, Inc. of Sunnyvale, Calif., such as the K7 microprocessor, have included a die crack detection chain. The chain runs the length of the L2 side of the die. The L2 side of the die is more vulnerable to cracks than other parts of the die. The chain one failure signature reliably indicates the presence of cracks on the L2 side of the die which has no input/output circuitry. However, the chain cannot detect cracks that occur on other portions of the die.
In addition, IC dies can be subject to delaminations. Delaminations occur when neighboring layers separate or pull apart from each other. Metal layers are particularly susceptible to delamination problems. Delamination can cause a disconnection between neighboring metal layers which results in an IC device failure. As the metal layers are separated from each other due to delamination, conductive vias in the neighboring layers no longer contact the conductive lines above or below them. Heretofore, delaminations have been difficult to detect.
Therefore, there is a need for a structure for and a method of detecting cracks and/or delamination in a production chip. Further still, there is a need for a structure for and a method of detecting cracks across an entire IC die and/or delaminations in the IC die. Yet further, there is a need for a structure for and method of quickly diagnosing chip cracks and/or delaminations and using that data to derive corrective actions. Yet even further, there is a need for and a method of detecting a crack across the entire periphery of the IC die or delaminations in a metal layer of the IC die. Yet further, there is a need for a circuit that can diagnose the mechanical health of the IC die.